This invention relates generally to techniques for digitally quantizing a signal and, more particularly, to quantizers such as analog-to-digital (A/D) converters of the flash or fully parallel type.
In flash or parallel A/D conversion, an analog signal is applied to multiple identical comparators, one for each possible quantization level. For a device producing an n-bit digital output word, there are 2.sup.n possible quantization levels and one fewer comparators. For example, an eight-bit A/D converter would have 2.sup.8 -1 (=255) comparators. Each comparator receives two inputs. The analog input signal to be converted is applied to each of the comparators, and the other comparator inputs are tied to different, normally equally spaced voltages, usually derived from a reference resistance ladder. When a "convert" signal is applied to the comparators, each one tied to a reference voltage higher than the analog input signal produces a "1" output signal, and each one tied to a reference voltage below the analog input signal produces a "0" output signal. The resultant outputs are sometimes referred to as a "thermometer code" of "1's" and "0's" arrayed on each side of a transition point representing the analog input signal. The location of this transition is decoded to produce a digital output quantity equivalent to the analog input signal.
A critical problem in manufacturing these devices in monolithic form is that the comparators are sometimes not perfect. Transistor mismatches generate input offset voltages which effectively move the transition points of the comparators. For example, a comparator may switch (from "1" to "0" output) when the difference between its input voltages is 8 millivolts instead of zero. This type of defect generates unacceptable performance in a flash A/D converter if a large (8 millivolts) mismatch occurs in any one of the comparators. In practice, such defects are detected during testing, and devices with any significant defects are rejected, but the problem can have the effect of drastically reducing the yield of acceptable devices. Another effect of transistor mismatches is that higher speed wafer fabrication processes cannot be used to manufacture flash A/D converters, because fast processes typically have poor matching characteristics.
A transistor mismatch affects the linearity of the A/D converter. The transfer function of an A/D converter looks like a staircase. There are two roughly independent measurements of the linearity of this transfer function. Differential linearity refers to the uniformity of the step sizes. Any transistor mismatch will generate a larger or smaller step, causing a differential non-linearity at that comparator. Integral linearity refers to the worst case deviation from a straight line (ignoring the inevitable 1/2 steps). Although integral linearity is normally a measure of the overall bow of the transfer function, uneven step sizes due to transistor mismatches can be the dominant source of integral non-linearity.
Prior to this invention, transistor mismatch problems have, for the most part, been addressed by using parallel devices. In areas of the comparator circuit known to be most sensitive to mismatch, each transistor is duplicated by one or more identical transistors which are connected in parallel: collector to collector, base to base, and emitter to emitter. If any one transistor contains a defect, the mismatch effect will be reduced by the presence of parallel transistors without defects. A commonly used equivalent technique is simply to enlarge the sensitive devices. The costs of these approaches are the increase in size of the A/D converter, and the increase in the power required to drive the larger capacitors at high speeds.
A variant of the parallel transistor approach is called the "common centroid" scheme, in which the positions of the various paralleled transistors are utilized to further reduce mismatches. Two pairs of paralleled transistors are arranged in a square configuration, with the members of each pair being diagonally opposed, such that the centers of the pairs fall at the common center of the square. This scheme enhances the simple parallel transistor approach in situations in which the mismatches do not occur randomly, but in linear gradients across the device.
There is a technique known as analog interpolation, which has a coincidental similarity of structure that necessitates its discussion here. Analog interpolation is discussed in a paper entitled "An 8-bit Video ADC Incorporating Folding and Interpolation Techniques," by Rob E. J. Van de Grift et al., IEEE J. of Solid-State Circuits, Vol. SC-22, No. 6, pp. 944-953, Dec. 1987. The object of the interpolation scheme proposed in the paper is to reduce the number of input amplifiers used in the comparators. Large numbers of input amplifiers provide an undesirably high input capacitance, so the authors of this paper proposed a scheme in which many of the input amplifers are omitted entirely. However, if the device is to retain the same resolution as one with a full complement of input amplifiers, the outputs of the missing amplifiers have to be provided by some means. The following discussion assumes an interpolation factor of two. The technique suggested is that the output of a missing amplifier is provided by averaging the outputs of two adjacent amplifiers, on each side of the missing amplifier. Thus, although the number of input amplifiers is reduced by a factor of two in this case, a complete set of equivalent amplifier output signals is obtained by interpolating between each adjacent pair of available amplifier outputs. In other words, it is assumed that each missing amplifier output is midway between the outputs of the amplifiers on each side of the missing one. The circuit described in the paper mentioned above actually utilizes an interpolation factor of 4, where 3 out of 4 amplifiers are omitted and surrogate output waveforms are reconstructed from the remaining amplifiers. Again, the goals of interpolation are to reduce both the input capacitance and component count of the A/D converter.
A pleasant side effect of interpolation is an improvement in differential linearity. This occurs because any transistor mismatch which occurs in one of the remaining amplifiers affects the step size of more than one comparator. Thus, instead of causing a single large error, the effect of the mismatch is distributed as smaller errors over a larger number of comparators. For example, if an amplifier has a transistor mismatch equal to the size of the quantization step, then that comparator would have a 1 least significant bit (LSB) error. With an interpolation factor of 4, the next comparator down would have a 3/4 LSB error, followed by 1/2 LSB and 1/4 LSB in the next comparators. Note that the step size from a 1 LSB to a 3/4 LSB error is 1/4 LSB. Thus the single large error is translated into 4 errors of 1/4 size each, resulting in a factor of 4 improvement in differential linearity. However, interpolation does not reduce the effect of a transistor mismatch on integral linearity. In the example above, the integral non-linearity is 1 LSB, unaffected by the interpolation.
It will be appreciated from the foregoing that another technique is needed to reduce the effects of transistor mismatches. The new technique should avoid the large number of components and the speed penalty associated with parallel devices, and should improve integral linearity unlike interpolation. The present invention achieves this goal, as will become apparent from the following summary.